Requirement of network capacity

Requirement of network capacity is increasing du

Optical Packet Switch Architectures Evaluation using Optical Cost and Physical Loss Preeti Singh Department of ECE, ASET, Amity University, Uttar Pradesh, Noida, India Email: s23.preeti@gmail.com J. K. Rai Department of ECE, ASET, Amity University, Uttar Pradesh, Noida, India Email: jkraius@rediffmail.com Ajay K Sharma National Institute of Technology Delhi, India Delhi, India Email: director@nitdelhi.ac.in AbstractRequirement of network capacity is increasing due to growing demand of internet traffic. Data centre network traffic is boosting steadily due to arising mobile, internet and cloud services. In this paper four photonic packet switched architectures namely feedback loop buffer and arrayed waveguide grating (AWG) based switch, loss compensated feedback loop buffer and AWG based switch, electronic memory and AWG based optical switch, and buffer less optical Switch PETABIT have been analysed for their optical cost and physical loss. Cost of these architectures has been evaluated using fiber-to-chip coupling (FCC) and wavelength speed-up model (WSU). FCC model assumes fixed cost and doesnt account for wavelength conversion range. To include the influence of wavelength conversion range WSU model has been used. Optical cost itself may not reflect the true performance of the architecture so physical loss of these architectures has also been estimated. The results of this work shows that the optical cost of electronic memory and AWG based optical switch is the least but its physical loss is the highest and for buffer less optical Switch PETABIT it is vice-versa. Also the optical cost and physical loss of feedback loop buffer and AWG based switch, and loss compensated feedback loop buffer and AWG based switch are almost similar. So, feedback loop buffer and AWG based switch is better among the architectures explored in this work. Index TermsArrayed waveguide grating, fiber-to-chip coupling, fiber delay lines, tunable wavelength converter, wavelength speed-up. I. INTRODUCTION Internet traffic is growing exponentially because of emerging applications like social networking, video streaming, cloud computing etc. and hence more powerful Data Centers (DCs) are required.These DCs interact with outer world, web and data-base servers. Due to continuous demand of the network services, requirement for higher bandwidth is rising. Electronic devices cannot cater the demand for higher bandwidth because of speed constraints and hence all optical technology plays a significant role [1]. To meet this enhanced demand in the communication networks, fiber optic and photonic technology is being explored nowadays. A promising technique is an optical packet switched (OPS) network. Optical switching demands for all optical implementation of all the switching functions. The network structure constitutes of core and client networks. Edge routers act as an interface between client and core network. Control and processing units are difficult to implement in optical domain and is technically not feasible, therefore most of the optical switch architectures are hybrid in nature [2]. In these switch architectures buffering and switching of the packets are done optically, while control is implemented in the electronic domain. Continuous growth of telecommunication infrastructure driven by the rapid expansion of the volume of internet traffic requires development of new switching and transmission equipment. Performance of optical switch is measured in terms of physical and network layer parameters. Moreover, in optical switching systems there are countless attributes that affect the switch performance. First compact model useful in evaluation of optical cost of switch architecture is proposed in [3]. This model is based on Fiber-to-Chip Coupling (FCC) which is the number of interconnections to the outer world through the component. This model assumes fixed cost i.e. only the input and output number of fibers of the device are considered. Wavelength conversion range is not included in FCC model. A heuristic cost model, Wavelength Speed-Up (WSU), is proposed in [4] to incorporate the effect of wavelength conversion. This paper presents an evaluation methodology carried out on four OPS architectures based on their optical cost and physical loss. Optical cost has been estimated using both FCC and WSU model. Optical cost is not sufficient to analyze an architecture and does not reflect the performance of the architecture. Physical loss of optical switches is an important parameter to analyse the performance of the switch. Hence physical loss have also been estimated for evaluation of OPS architectures. Insertion loss of each device has been considered in evaluating the physical loss of the architectures. Rest of the paper is organized as follows. Section II describes the architectures of the four OPS architectures evaluated in this work. Section III describes cost analysis of the architectures using FCC and WSU model. In Section IV physical loss of the architectures are estimated. Results are presented in Section V and finally, conclusion and future scope are presented in section VI. II. ARCHITECTURES DESCRIPTION Four OPS architectures evaluated in this paper are described below: IEEE 40222 8th ICCCNT 2017 July 3 5, 2017, IIT Delhi, Delhi, India A. Feedback Loop Buffer and Arrayed Waveguide Grating (AWG) based Switch (Architecture A1) Feedback Fiber Delay Lines (FDL) and AWG based OPS architecture (Architecture A1) is shown in Fig. 1. This architecture comprises of two sections namely, scheduling and switching section. Scheduling section consists of 2N 2N AWG router as its core component and the switching section consists of an N N AWG router [5]. N buffer modules are connected to the upper N ports numbered 1 to N of the AWG router of the scheduling section. Input ports equipped with Tunable Wavelength Converters (TWCs) are connected to the lower port i.e. port N + 1 to 2N of the AWG router in scheduling section. TWCs placed at the inputs of the switch tunes the wavelength of incoming packets as per the buffer status and desired output ports. Lower ports (N + 1 to 2N) of AWG are actual input/output ports. This architecture uses WDM for storage of packets in different fiber loop modules altogether called the buffer loop. The number of modules in the buffer loop are determined by the desired traffic throughput, average delay etc. Only one packet is stored in an buffer module for an output port. Fig. 1. Schematic of architecture A1 B. Loss Compensated Feedback Loop Buffer and AWG based Switch (Architecture A2) In architecture A1 the buffered packets suffer loss as it passes through the buffer module. To overcome this shortcoming, design alteration is made in architecture A1. As an alteration in each branch of the buffer Semiconductor Optical Amplifier (SOA) is placed as shown in Fig. 2. SOA is a device whose gain can be adjusted as per the requirement. The loss occurring in each fiber loop module will be different, due to unequal lengths of the loops and can be compensated by a variable gain SOA [6]. This modification ensures that the received packet at the output of the switch has identical optical power. Fig. 2. Schematic of architecture A2 C. Electronic Memory and AWG based Optical Switch (Architecture A3) Data Center Optical Switch (DCOS) is an optical burst switch with shared electronic buffers for DC [7]. Fig. 3 depicts the architecture A3 of one such switch. The idea is to use a single AWG for supporting flattened DC network topology. In Fig. 3, an N N AWG is used to connect N 1 source nodes to N 1 destination nodes and one last AWG port is dedicated for buffering. The key concept used in this architecture is that due to cyclic routing pattern of the AWG, multiple inputs can connect to the same output simultaneously. If more than one packet is destined to a given output port, contention is inevitable. The packets that could not gain access to their desired output port needs a mechanism to be stored, so that they can be retransmitted later. Packet drop is more critical in DC applications. Hence, the scheduler has to direct some of these packets to a shared Synchronous Dynamic Random Access Memory (SDRAM) buffer. TWC TWC TWC SDRAM Buffer E/O O/E E/O E/O O/E O/E AWG N-1 N-2 1 2 1 2 N-2 N-1 N N TWC Fig. 3. Schematic of architecture A3 Loop back buffer system comprised of optical multiIEEE 40222 8th ICCCNT 2017 July 3 5, 2017, IIT Delhi, Delhi, India plexer and demultiplexer, electrical-to-optical (E/O) converters, optical-to-electrical (O/E) converters, and SDRAM buffer. Failed packets are received by the shared SDRAM buffer. E/O converters are connected to the multiple outputs of shared SDRAM buffer. Hence, the scheduler has to direct some of these packets to a shared SDRAM buffer. Since there exists N internal AWG wavelengths, a 1 N optical demultiplexers is used to separate the contending bursts on the loopback fiber. O/E converters follow the demultiplexer to convert the optical bursts into electrical signals for storage in SDRAM buffer. Whenever a buffered burst finds the chance to be dispatched to its desired destination, it is converted back to an optical signal and forwarded through the switch fabric. D. Bufferless Optical Switch PETABIT (Architecture A4) The block diagram of Bufferless Optical Switch PETABIT Architecture A4 is depicted in Fig. 4 [8]. It adopts a three stage topology of Input Module (IM), Central Module (CM) and Output Modules (OM). AWG router (AWGR) is used as the core component by each module. Tunable lasers are used to route the packets through the AWGRs in the first stage, while TWC are used to convert the wavelength and route the packets accordingly to target port in the second and third stage. Fig. 4. Schematic of architecture A4 III. COST ANALYSIS OF OPTICAL PACKET SWITCH ARCHITECTURES In this section, optical cost of the architectures described in Section II is estimated. Optical cost of a node is sum of costs of all optical components used to construct the node. Number of FCC for respective optical components in the node is used to estimate the optical cost of four architectures as done in [9]. As this model anticipates fixed cost for active and passive devices, the TWCs cost that can be tuned with wavelengths is assumed to be 4 (3 input fiber + 1 output fiber) [10]. Table I shows the optical cost of various components using FCC method. To overcome the fixed cost drawback of FCC model, WSU model is used [4]. Cost of TWCs is given by (1). CT W C = (1) where, is a normalization constant, is the conversion range. TABLE I OPTICAL COST OF THE COMPONENTS USING FCC METHOD Symbol Component Cost CDemux(N1) Demux N+1 N+1 2 2N 2 2 2 2 4 CMux(1N) CSOA CAWG(NN) CO/E CE/O CMem CF DL CTWC Mux SOA AWG O/E E/O Memory FDL TWC Thus, cost of the TWCs which can be tuned up to wavelength is given by (2). CT W C = (2) This model assumes linear trend between cost and range of the tunable wavelength. A comparatively more generalized model proposed in [11] specifies the cost of TWCs given by (3). CT W C = b (3) where, is a normalization constant and its maximum value can be 1, is the conversion range and b is wavelength speedup factor which takes into account the tunability range of TWC and its value lies between 0.5 to 5 [11]. A more cost effective model for wavelength speed up factor in the range of 0.5 to 1 is proposed in [5]. Cost of the TWCs which can be tuned up to wavelengths is given by (4). CT W C = , b, > = 11 (4) Hence cost of TWCs as given in (4) is used in this work for WSU model. A. Cost Estimation of the Architectures Costs of four architectures have been estimated by including cost of all the devices needed to realize the architecture. Cost of architectures A1, A2, A3 and A4 can be computed by using (5) (8) respectively. CA1 = NCT W C + CAWG(2N2N) + NCT W C + CAWG(NN) + NCF DL = NCT W C + CAWG(2N2N) + NCT W C + CAWG(NN)NCF DL + NCSOA = (N 1)CT W C + CAWG(NN) + NCO/E + NCE/O + CMem + CMux + CDemux = 6CAWG(NN) + 4NCT W C (5) CA2 (6) CA3 (7) (8) CA4 IEEE 40222 8th ICCCNT 2017 July 3 5, 2017, IIT Delhi, Delhi, India Taking in account the FCC cost from Table I for various components, cost of these architectures are given by (9) (12). C A1 (9) CF CC A2 (10) CF CC A3 = 4(N 1) + 2N + 2N + 2N + 2N + N + 1 + N + 1 = 4(N 1) + 10N + 2 (11) CF CC A4 = 6 2N + 4(4N) = 28N (12) F CC = 4N + 4N + 4N + 2N + 2N = 16N = 4N + 4N + 4N + 2N + 2N + 2N = 18N Cost of the four architectures using WSU model given by (4), is computed using (5) (8) and is given in (14) (16). CW SU b + N(N)b + 8N (13) A1 = N(2N) CAW SU 2 = N(2N)b + N(N)b + 10N (14) CAW SU 3 = (N 1)(N)b + 10N + 2 (15) CAW SU 4 = 6 2N + 4N(N)b (16) IV. PHYSICAL LOSS OF ARCHITECTURES Physical loss of optical switches is an important parameter for performance analysis of the switch. It is defined as the insertion loss of a device. Total loss of a switch is estimated by considering the loss of all devices needed to realize the switch. From the mathematical abstraction point of view the switches can be divided into three distinct parts namely input unit (Lin), buffer unit (Lb) and output unit (Lout) [12]. LT = Lin + Lb + Lout (17) A. Loss estimate of architecture A1 Loss of input unit, buffer unit and output unit is given by (18), (19) and (20) respectively and total loss of architecture A1 is obtained by adding the loss of three units and is given by (21). Lin = LT W C (18) (19) (20) Lb = LAWG(2N2N) + LF DL Lout = LAWG(2N2N) + LT W C + LAWG(NN) LT = Lin + Lb + Lout = LT W C + LAWG(2N2N) + LF DL + LAWG(2N2N) + LT W C + LAWG(NN) (21) B. Loss estimate of architecture A2 Loss of input unit, buffer unit and output is given by (22), (23) and (24) respectively and total loss of architecture A2 is obtained by adding the loss of three units and is given by (25). Lin Lb Lout = LT W C = LAWG(2N2N) + LF DL + LSOA = LAWG(2N2N) + LT W C + LAWG(NN) (22) (23) (24) LT = Lin + Lb + Lout = LT W C + LAWG(2N2N) + LF DL + LSOA + LAWG(2N2N) + LT W C + LAWG(NN) (25) C. Loss estimate of architecture A3 Loss of input unit, buffer unit and output is given by (26), (27) and (28) respectively and total loss of architecture A3 is obtained by adding the loss of three units and is given by (29). Lin = LT W C (26) Lb = LAWG(NN) + LDemux + LO/E + LE/O + LMem + LDemux + LAWG(NN) = LAWG(NN) (27) (28) Lout LT = Lin + Lb + Lout = LT W C + LAWG(NN) + LDemux + LO/E + LE/O + LMem + LDemux + LAWG(NN) + LAWG(NN) (29) D. Loss estimate of architecture A4 Loss of input module, center module and output module is given by (30), (31) and (32) respectively and total loss of architecture A4 is obtained by adding the loss of three units and is given by (33). Lim Lcm Lom = LAWG(NN) = LT W C + LAWG(NN) = LT W C + LAWG(NN) (30) (31) (32) LT = Lin + Lb + Lout = LT W C + LAWG(NN) + LAWG(NN) + LT W C + LAWG(NN) V. RESULTS (33) Cost of the four architectures have been estimated using the methodology described in section III. Fig. 5 shows the cost of the architectures obtained using FCC model. It can be observed from Fig. 5 that the cost of architecture A4 is highest and A3 is lowest. The cost increases linearly with increase in N as is evident from (9) (12). Also it can be observed that with increase in N the cost of architecture A4 increases at much higher rate than the remaining three architectures as more number of components have been used in architecture A4. Fig. 6 9 shows the cost of architectures A1 A4 respectively using WSU model. It can be observed that the cost of architectures increases exponentially with increase in number of TWCs. The cost increases abruptly for architectures A1, A2 and A4 for N greater than 4. A4 is having the larger number of TWCs so its cost is rising at higher rate. The variation in cost of architecture A3 is less as it is having less number of TWCs. The cost estimation by FCC and WSU model clearly IEEE 40222 8th ICCCNT 2017 July 3 5, 2017, IIT Delhi, Delhi, India Fig. 5. Cost of architectures using FCC method. 0 20 40 60 80 0 5000 10000 15000 N cost b=1 b=0.9 b=0.8 b=0.7 b=0.6 Fig. 6. WSU cost for architecture A1 0 20 40 60 80 0 5000 10000 15000 N cost b=1 b b=0.8 b=0.7 b=0.6 Fig. 7. WSU cost for architecture A2 indicates that the cost in case of FCC model is quite low and fixed in comparison to WSU model. Physical loss of the four architectures have been estimated using (21), (25), (29) and (33). Loss for individual components is given in Table II [13], [14]. Table III shows the physical loss estimate for architectures A1, A2, A3 and A4. Physical loss for architectures A1, A2 and A4 is independent of size (N) of the switches. Loss of architecture A3 depends on size of multiplexers and demultiplexers used in 0 20 40 60 80 0 1000 2000 3000 4000 5000 N cost b=1 b=0.9 b=0.8 b=0.7 b=0.6 Fig. 8. WSU cost for architecture A3 0 20 40 60 80 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 N cost b=1 b=0.9 b=0.8 b=0.7 b=0.6 Fig. 9. WSU cost for architecture A4 TABLE II LOSS OF DIFFERENT COMPONENTS Parameter-loss Value TWC [13] 2.0 dB SOA [13] 1.0 dB Demultiplexer [14] 1.5 (N=4), 3 (N=16) dB Multiplexer [14] 1.5 (N=4), 3 (N=16) dB FDL [13] .2 dB/km AWG [13] 3 dB Mem [13] 2 dB E/O [13] 1 dB O/E [13] 1 dB loop back buffer system. At present optical multiplexers and demultiplexers are available only up to 40 channels. So the loss estimate for architecture A3 has been carried out only up to 40 channels. It can be observed from Table III that architecture A4 is having the least physical loss but its optical cost is the maximum. Similarly, cost of architecture A3 is least but the loss is maximum. So, out of the architectures A1 and A2 with almost similar cost and loss additional parameters will be explored further to find out an evaluative strategy for switch architectures. IEEE 40222 8th ICCCNT 2017 July 3 5, 2017, IIT Delhi, Delhi, India TABLE III LOSS OF ARCHITECURES Architecture Loss (dB) A1 13.2 A2 14.2 A3 18 (N 4), 21 (4

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